1. Technical Field
The present invention relates to a fringe field switching (FFS) mode liquid crystal display panel in which a pixel electrode and a common electrode are arranged on a planar film, so as to prevent a problem such as an increase in wiring resistance due to disconnection and corrosion, while various members are mounted on a mounting terminal portion, and a manufacturing method thereof.
2. Related Art
Vertical electric field type liquid crystal display panels that include a pair of transparent substrates formed with an electrode and the like on the surface and a liquid crystal layer sandwiched between the pair of substrates, which display various pieces of information by rearranging liquid crystals by applying voltage to the electrodes on both substrates, have been widely used. Typical vertical electric field type liquid crystal display panels are in a twisted nematic (TN) mode, but because there is the problem of a narrow viewing angle, various improved vertical electric field type liquid crystal display panels such as a vertical alignment (VA) mode and a multi-domain vertical alignment (MVA) mode have been developed.
In addition to the above-described vertical electric field type liquid crystal display panel, a liquid crystal display panel in an in-plane switching (IPS) mode or a FFS mode, which is also known as a transverse electric field type liquid crystal display panel that provides a pair of electrodes formed of a pixel electrode and a common electrode only on one substrate, is also known.
The IPS mode liquid crystal display panel disposes a pair of electrodes on the same layer, and rearranges liquid crystal molecules in a direction parallel to a substrate, by setting the direction of the electric field applied to the liquid crystal as the direction substantially parallel to the substrate. Therefore, the IPS mode liquid crystal display panel has an advantage of having an extremely wide viewing angle compared to the above described vertical electric field type liquid crystal display panel. However, in the IPS mode liquid crystal display panel, a pair of electrodes is provided on the same layer to apply the electric field to the liquid crystal. Accordingly, the liquid crystal molecules placed at the upper side of the pixel electrode are not fully driven, thereby causing a problem such as low transmittance.
To solve such a problem of IPS mode liquid crystal display panels, FFS mode liquid crystal display panels have been developed (see JP-A-2001-235763 and JP-A-2002-182230). In FFS mode liquid crystal display panels, the pixel electrode and the common electrode are disposed to apply the electric field to the liquid crystal layer, on the different layers with an insulator interposed therebetween. FFS mode liquid crystal displays panel have a wider viewing angle and a higher contrast than IPS mode liquid crystal display panels, are capable of operating at low voltage, and allow a brighter display due to their higher transmittance. In addition, in an FFS mode liquid crystal display panel, because an overlapping area between the pixel electrode and the common electrode is larger than that of the IPS mode liquid crystal display panel in planar view, there is an advantage of secondarily generating a larger storage capacitance, thereby eliminating the need to provide a separate auxiliary capacitor line.
A configuration of a mounting terminal portion formed at a periphery of a related art liquid crystal display panel will now be explained with reference to FIGS. 8A and 8B.
FIG. 8A is a sectional view of a related art mounting terminal portion of a lower wiring, and FIG. 8B is a sectional view of a related art mounting terminal portion of an upper wiring.
The manufacturing of the mounting terminal portion is performed simultaneously with the manufacturing of scanning lines or signal lines in an array substrate of the liquid crystal display panel. Therefore, there are a mounting terminal portion connected to a lower wiring 52 simultaneously manufactured with the manufacturing of the scanning lines and a gate electrode on a transparent substrate 51, as shown in FIG. 8A, and a mounting terminal portion connected to an upper wiring 54 formed simultaneously with the signal lines on a gate insulator 53 that covers the surface of the transparent substrate 51, as shown in FIG. 8B. The surfaces of the upper wiring 54 and the gate insulator 53 are covered with a passivation film (also referred to as protective insulator) 55.
A mounting terminal 56 for the lower wiring 52, as shown in FIG. 8A, is formed of a transparent conductive material, via a contact hole 57 formed so as to simultaneously penetrate through the passivation film 55 and the gate insulator 53, at the same time when the pixel electrode is formed. Similarly, a mounting terminal 58 for the upper wiring 54, as shown in FIG. 8B, is formed of the transparent conductive material via a contact hole 59 formed so as to penetrate through the passivation film 55, at the same time when the pixel electrode is formed. Therefore, the lower wiring 52 and the upper wiring 54 are exposed to an etching atmosphere once, while the contact holes 57 and 59 are formed by using photolithography. The mounting terminals 56 and 58 for the lower wiring 52 and the upper wiring 54 formed in this manner, are respectively provided at higher positions than the lower wiring 52 and the upper wiring 54, and provided so as the widths are larger than those of the lower wiring 52 and the upper wiring 54, thereby improving electrical contact with various connecting members connected to the mounting terminals 56 and 58.
With the related art FFS mode liquid crystal display panel, a step is formed on the surface of the pixel electrode overlapping with a switching element such as a thin film transistor (TFT) and a common line, thereby disturbing the alignment of the liquid crystal molecules at the step portion. Consequently, in the related art FFS mode liquid crystal display panel, because the step portion is a region that does not actually contribute to the display, the step portion is shielded by a black matrix on a color filter substrate, thereby reducing aperture ratio just as much as the step.
To eliminate such a step, by using a planar film used in the liquid crystal display panel in the VA mode and the MVA mode, the pixel electrode and the common electrode may be disposed on the planar film. However, if such a configuration is adopted in the FFS mode liquid crystal display panel, on the planar film, the pixel electrode and the common electrode are respectively disposed on different layers with an insulator interposed therebetween. Accordingly, the insulator formed on the surface of the lower wiring or the upper wiring is increased by one layer, while the mounting terminal portion is formed at the periphery. A process of simultaneously forming the contact hole in the pixel portion, while forming the contact hole to expose the lower wiring or the upper wiring of the mounting terminal portion, by using photolithography, will be now explained. An opening portion is formed in a gate insulator (nitride film) and a protective film (nitride film) layered at a contact hole forming position of the mounting terminal portion, and after a common electrode is formed on the planar film layered excluding the mounting terminal portion, an insulator (nitride film) is layered on the entire surface. An opening portion is then again formed and penetrated through to a potential line, at the contact hole forming position of the mounting terminal portion. While forming the pixel electrode in the pixel portion, an electrode made of the same material as the common electrode is formed in the contact hole of the mounting terminal portion. However, in this method, the lower wiring or the upper wiring are exposed to the etching atmosphere as much as twice.
Because the lower wiring and the upper wiring are formed of metal with good conductivity but susceptible to corrosion, such as aluminum or aluminum alloy, the damage is increased when the lower wiring and the upper wiring are exposed to the etching atmosphere of the insulator, as much as twice. Accordingly, a problem such as an increase in wiring resistance due to disconnection and corrosion may occur while being mounted.
Therefore, each electrode wiring is prevented from being exposed to the etching atmosphere by, rather than providing an opening to the gate insulator (nitride film) and the protective film (nitride film) at the contact hole disposing position of the mounting terminal portion while the contact hole of the pixel electrode is being opened, but by etching the contact holes of the mounting terminal portion in bulk after the insulator interposed between the pixel electrode and the common electrode is formed. However, with this process, because the film quality between the insulator, and the gate insulator and the protective film differ, thereby having different etching rates. Consequently, problems occur in that the insulator is formed in a reverse taper shape, a step is generated between respective nitride films, a step disconnection occurs while the contact portion is covered by the upper electrode, which prevents them from being in contact with one another.